Reed Solomon Decoder: TMS320C64x Implementation

This application report describes a Reed Solomon decoder implementation on the TMS320C64x DSP family. Reed Solomon codes have been widely accepted as the preferred (ECC) error control coding scheme for ADSL networks, digital cellular phones and high-definition television systems. The reason for their widespread prevalence is their excellent robustness to burst errors. Programmable implementations of the Reed Solomon decoder offer the system designer the unique flexibility to trade off the data bandwidth and vary the error correcting capability that is desired for a given channel. An efficient method to perform Reed Solomon decoding is the Peteren-Gorenstein-Zierler (PGZ) algorithm. Digital signal processors of the TMS320C6000 DSP platform seek to exploit the data level and instruction level parallelism of algorithms by having multiple ALU units capable of working in tandem, to obtain extremely high levels of performance. The advanced set of code generation tools help the user in identifying the parallelism in the decoding algorithm for the multiple units of the DSP to exploit. This application note helps to overcome this challenge by showing the steps involved in the developing an efficient implementation of a complete (204,188,8) Reed Solomon decoder on the TMS320C64x DSP family. This application report • Identifies the various processing steps that are involved in the development of a Reed Solomon decoder. • Discusses the instructions and features of the C6400 DSP used for implementing an efficient Reed Solomon decoder. • Presents a complete implementation of a (204,188,8) Reed Solomon decoder on the C6400 DSP.